1. Field of the Invention
The present invention relates generally to digital phase detectors and, more particularly, to digital phase detectors having tolerance for duty cycle distortion and clock skew.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Digital phase detectors (DPDs) are widely used to compare the respective phases of two input signals. For instance, DPDs may be used in synchronization circuits, such as delay lock loops (DLLs) or phase lock loops (PLLs), to compare input signals such that they may be synchronized or “locked.” By comparing a reference signal, such as a clock signal, to a feedback signal using a DPD, phase adjustments may be made to one or both of the input signals based on the comparison of the input signals, in order to synchronize the signals. As will be appreciated, synchronization of certain signals within a device or system is often advantageous. In alternate applications, phase detectors may also be used to for duty cycle correction and in calibration circuits, for instance.
As will be appreciated, phase detectors are generally configured to provide a certain period of time known as the “lock window” or “detection window” to indicate when the input signals are synchronized or locked. A lock window may be implemented to account for set-up time and process voltage temperature (PVT) variations. At high speeds, the input signals may become distorted and the duty cycle may become something other than a 50% duty cycle. Once the speed of the input signal, which may be a clock signal, exceeds 1 GHz, the lock window, which may be on the order of 300 picoseconds to 400 picoseconds, may encompass 30-40% of the entire duty cycle. Thus, as clock speeds increase, clock skew and duty cycle distortion have an increasingly proportionate impact on phase locking. For high-speed operations, duty cycle distortion and clock skew may adversely affect synchronization. Disadvantageously, the clock skew and duty cycle distortion may be such that in high-speed operation, a device receiving output signals from the DPD which have been produced based on distorted or skewed input signals, may incorrectly adjust one or both of the input signals based on an erroneous output from the DPD. By adjusting one or both of the phases of the input signals in the wrong direction, the locking time may be disadvantageously increased.
Embodiments of the present invention may address one or more of the problems set forth above.